Improvement S B ox of AES A lgorithm B ased on FPGA

Abstract

AES is the most mainstream and common encryption standard in the 21st century. It has the advantages of high efficiency, good stability and strong flexibility. It is widely used in e - commerce, encryption hard disk and network transmission encryption. However, in recent years, some AES algorithm has been attacked, which is exposing its S - box simple, single - key and other defects, so the traditional AES algorithm ought to be further improved. Based on FPGA technology, this paper designs and designs a secure processor model of chaotic neural network, realizes the chaotic characteristics of S - box and improves the ability of anti - attack system. The system has the advantages of good reconfiguration, simple circuit structure, low resource consumption and fast running speed, and has good practicability and good application prospect in security encryption and other fields .