A Hardware Design of High-throughput and Resource-saving Image Convolution

Abstract

This paper proposes a hardware design of high-throughput and resource-saving image convolution. The key part of the design is consist of two aspects, buffer and computing part. For the buffer part, serial shifting register chain has been applied to buffer some of the pixels so that large number of buffer resources could be saved, thus realizing data multiplex; as for computing part, logic resource consumed is not much but time consumed for the serial convolution operation is too long. Since buffer part consumes little resource, logic duplication can be used to realize parallel design, thus accelerating the convolution operation, which reduces the time consumed largely and makes the throughput higher. In one word, this design not only accelerates the convolution operation, but also reduces the consumed resources.