A DPLL-based High-Concurrent SAT Solver with FPGA

Abstract

The SAT problem is one of the most famous NP problems in the theoretical studies of computer science that has been applied in a number of areas, such as artificial intelligence and emulation; and then its high efficient solver, both software and hardware, drives both the study and application of SAT problem. It is well known that the hardware-based solution of SAT solver is capacitated by the high speed, but the design complexity and long chain flow refuse researcher’s enthusiasm. In this article, we propose a FPGA-based SAT solver.